FIG. 1 depicts a programmable function unit (PFU) (also termed in the art a configurable logic block).
Reference numeral 13 denotes an 8-bit look-up table which has three inputs denoted by reference numerals 19, 21, and 23, respectively A.sub.0, B.sub.0, and the output of multiplexer 15. Multiplexer 15 receives inputs C.sub.in and C.sub.0 denoted by reference numerals 17 and 35, respectively. The output of look-up table 13 is carried on line 25, denoted by Output.sub.0.
Look-up table 13 is pre-programmed to perform a predetermined function of the three inputs on lines 19, 21 and 23, and to provide an output designated Output.sub.0 on line 25. In general look-up tables, such as table 13, perform general combinatorial or control logic, RAM or data path functions based upon the inputs A.sub.0, B.sub.0 and C.sub.0. If desired, additional inputs to look-up table (LUT) 13 may be provided, and the size of the look-up table increased. For example, if one more input is provided, the LUT 13 may be a 16 bit LUT.
In order to increase the speed of data path functions, fast-carry logic is implemented. This hard-wired fast-carry operation is provided by a hard-wired logic 27 which has three inputs A.sub.0 and B.sub.0 and C.sub.in, reference numerals 19, 21 and 17, respectively. This hard-wired carry logic 27 may also receive additional signals used to implement higher-level functions. Also, in this mode (termed a "ripple mode") multiplexer 15 selects C.sub.in as the third input to LUT 13. Thus, in the ripple mode, block 28 receives three inputs, A.sub.0 (19), B.sub.0 (21), and C.sub.in (17) and produces Output.sub.0 together with a carry-out signal 18 produced by hard-wired logic 27 as a function of A.sub.0 (19), B.sub.0 (21), and C.sub.in, (17). This carry-out signal may be used as the carry-in signal to the next block 29. Thus, each block, 28, can perform a single bit of a fast data path operation.
Similar functionality is provided in block 29 producing an Output.sub.1 denoted by reference numeral 31 and a carry output C.sub.out denoted by reference numeral 33. Generally, blocks such as 28, 29 can be cascaded as needed, thereby creating an n-bit data path function. Typical FPGA PFUs may contain one to eight blocks configured similar to block 28 and linked by carry signals in a manner akin to signal 18 between blocks 28 and 29.
The logic employed in reference numeral 27 is termed "fast-carry logic." One disadvantage to the configuration depicted in FIG. 1 is that the logic in block 27 is hard-wired. Consequently, there is no flexibility in determining the output (e.g., 18) of the fast-carry operation. In addition, logic function 27 may consume a significant amount of silicon real estate.